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| PSoCTM Mixed-Signal Array CY8C24123A, CY8C24223A, and CY8C24423A Final Data Sheet Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 2.4 to 5.25 V Operating Voltage Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) 6 Rail-to-Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 9-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 4 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Full-Duplex UART - Multiple SPITM Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 4K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 10 Analog Inputs on GPIO Two 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO New CY8C24x23A PSoC Device Derived from the CY8C24x23 Device Low Power and Low Voltage (2.4V) Additional System Resources I2CTM Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoCTM Designer) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Port 2 Port 1 Port 0 Analog Drivers PSoCTM Functional Overview The PSoCTM family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x23A family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks. PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller Global Analog Interconnect Flash 4K Sleep and Watchdog SROM CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array (1 Row, 4 Blocks) ANALOG SYSTEM Analog Block Array (2 Columns, 6 Blocks) Analog Ref Analog Input Muxing The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture micro- Digital Clocks Multiply Accum. POR and LVD Decimator I2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES September 8, 2004 (c) Cypress MicroSystems, Inc. 2004 -- Document No. 38-12028 Rev. *B 1 CY8C24x23A Final Data Sheet PSoCTM Overview processor. The CPU utilizes an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Digital peripheral configurations include those listed below. PWMs (8 to 32 bit) PWMs with Dead band (8 to 24 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 1) Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 3. The Analog System The Analog System is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below. The Digital System The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Port 1 Port 2 Port 0 Analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2 and 4 pole band-pass, low-pass, and notch) Amplifiers (up to 2, with selectable gain to 48x) Instrumentation amplifiers (1 with selectable gain to 93x) Comparators (up to 2, with 16 selectable thresholds) DACs (up to 2, with 6- to 9-bit resolution) Multiplying DACs (up to 2, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration 8 8 4 8 8 Row Output Configuration Row 0 DBB00 DBB01 DCB02 DCB03 4 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital System Block Diagram September 8, 2004 Document No. 38-12028 Rev. *B 2 CY8C24x23A Final Data Sheet PSoCTM Overview Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below. P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. P2[3] P2[4] P2[1] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACB00 ASC10 ASD20 ACB01 PSoC Device Characteristics ASD11 ASC21 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is shown in the next to the last row of the table. PSoC Device Characteristics Amount of SRAM Analog Columns Amount of Flash Analog Outputs Digital IO (max) Analog Blocks Analog Inputs Digital Blocks Digital Rows M8C Interface (Address Bus, Data Bus, Etc.) PSoC Device Group Analog System Block Diagram CY8C29x66 CY8C27x43 CY8C24x23 CY8C24x23A CY8C22x13 CY8C21x34 CY8C21x23 64 44 24 24 16 28 16 4 2 1 1 1 1 1 16 8 4 4 4 4 4 12 12 12 12 8 28 8 4 4 2 2 1 0 0 4 4 2 2 1 2 2 12 12 6 6 3 4a 4a 2 KB 256 Bytes 256 Bytes 256 Bytes 256 Bytes 512 Bytes 256 Bytes 32 KB 16 KB 4 KB 4 KB 2 KB 8 KB 4 KB a. Limited analog functionality. September 8, 2004 Document No. 38-12028 Rev. *B 3 CY8C24x23A Final Data Sheet PSoCTM Overview Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoCTM Mixed Signal Array Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc. Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view a current list of available items. Commands Tele-Training Free PSoC "Tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. Five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the tele-training, see http://www.cypress.com/support/training.cfm. PSoCTM Designer Graphical Designer Interface Context Sensitive Help Results Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site: http://www.cypress.com/support/cypros.cfm. PSoCTM Designer Core Engine Manufacturing Information File Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Application Notes A long list of application notes will assist you in every aspect of your design effort. To locate the PSoC application notes, go to http://www.cypress.com/design/results.cfm. Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Subsystems September 8, 2004 Document No. 38-12028 Rev. *B 4 CY8C24x23A Final Data Sheet PSoCTM Overview PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator Design Browser The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the parallel or USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. September 8, 2004 Document No. 38-12028 Rev. *B 5 CY8C24x23A Final Data Sheet PSoCTM Overview User Module Development Process The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Device Editor User Module Selection Placement and Parameterization Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. September 8, 2004 Document No. 38-12028 Rev. *B 6 CY8C24x23A Final Data Sheet PSoCTM Overview Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym Description Table of Contents For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed Signal Array Technical Reference Manual. This document encompasses and is organized into the following chapters and sections. 1. Pin Information ............................................................. 8 1.1 Pinouts ................................................................... 8 1.1.1 8-Pin Part Pinout ........................................ 8 1.1.2 20-Pin Part Pinout ...................................... 9 1.1.3 28-Pin Part Pinout .................................... 10 1.1.4 32-Pin Part Pinout .................................... 11 Register Reference ..................................................... 12 2.1 Register Conventions ........................................... 12 2.1.1 Abbreviations Used .................................. 12 2.2 Register Mapping Tables ..................................... 12 Electrical Specifications ............................................ 15 3.1 Absolute Maximum Ratings ................................ 16 3.2 Operating Temperature ....................................... 16 3.3 DC Electrical Characteristics ................................ 17 3.3.1 DC Chip-Level Specifications ................... 17 3.3.2 DC General Purpose IO Specifications .... 18 3.3.3 DC Operational Amplifier Specifications ... 19 3.3.4 DC Analog Output Buffer Specifications ... 22 3.3.5 DC Switch Mode Pump Specifications ..... 24 3.3.6 DC Analog Reference Specifications ....... 25 3.3.7 DC Analog PSoC Block Specifications ..... 26 3.3.8 DC POR, SMP, and LVD Specifications ... 27 3.3.9 DC Programming Specifications ............... 28 3.4 AC Electrical Characteristics ................................ 29 3.4.1 AC Chip-Level Specifications ................... 29 3.4.2 AC General Purpose IO Specifications .... 32 3.4.3 AC Operational Amplifier Specifications ... 33 3.4.4 AC Digital Block Specifications ................. 34 3.4.5 AC Analog Output Buffer Specifications ... 36 3.4.6 AC External Clock Specifications ............. 37 3.4.7 AC Programming Specifications ............... 38 3.4.8 AC I2C Specifications ............................... 39 Packaging Information ............................................... 40 4.1 Packaging Dimensions ......................................... 40 4.2 Thermal Impedances .......................................... 45 4.3 Capacitance on Crystal Pins ............................... 45 Ordering Information .................................................. 46 5.1 Ordering Code Definitions .................................... 46 Sales and Company Information ............................... 47 6.1 Revision History ................................................... 47 6.2 Copyrights and Code Protection .......................... 47 AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoCTM PWM SC SLIMO SMP SRAM alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor slow IMO switch mode pump static random access memory 2. 3. 4. Units of Measure A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 15 lists all the abbreviations used to measure the PSoC devices. 5. 6. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. September 8, 2004 Document No. 38-12028 Rev. *B 7 1. Pin Information This chapter describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 1.1.1 8-Pin Part Pinout Type Table 1-1. 8-Pin Part Pinout (PDIP, SOIC) Pin No. 1 2 3 4 5 6 7 8 IO IO IO Power I I Digital Analog Pin Name P0[5] P0[3] P1[1] Vss P1[0] P0[2] P0[4] Vdd Description Analog column mux input and column output. Analog column mux input and column output. Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Analog column mux input. Analog column mux input. Supply voltage. CY8C24123A 8-Pin PSoC Device AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1] Vss IO IO IO Power IO IO 8 1 2 PDIP7 3SOIC6 5 4 Vdd P0[4], AI P0[2], AI P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. September 8, 2004 Document No. 38-12028 Rev. *B 8 CY8C24x23A Final Data Sheet 1. Pin Information 1.1.2 20-Pin Part Pinout Type Table 1-2. 20-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO IO IO IO Power IO IO IO IO Input I I I I IO IO IO IO Power Digital Analog Pin Name P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL) I2C Serial Data (SDA) Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) Active high external reset with internal pull down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. CY8C24223A 20-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss IO IO IO IO Power I IO IO I 1 2 3 4 5 6 7 8 9 10 PDIP SSOP SOIC 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. September 8, 2004 Document No. 38-12028 Rev. *B 9 CY8C24x23A Final Data Sheet 1. Pin Information 1.1.3 28-Pin Part Pinout Type Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IO IO IO IO IO IO IO IO Power I I I I IO IO IO IO Input I I IO IO IO IO Power Digital Analog Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. CY8C24423A 28-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss IO IO IO IO IO IO IO IO Power I IO IO I I I P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL) I2C Serial Data (SDA) Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) External Voltage Reference (VRef) Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. September 8, 2004 Document No. 38-12028 Rev. *B 10 CY8C24x23A Final Data Sheet 1. Pin Information 1.1.4 32-Pin Part Pinout Type Table 1-4. 32-Pin Part Pinout (MLF*) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO IO IO IO IO IO Power I IO IO I I I IO IO IO IO IO IO I I IO Input I I IO IO IO IO IO Power IO IO Digital Analog Pin Name P2[7] P2[5] Description CY8C24423A 32-Pin PSoC Device P0[1], AI P0[3], AIO P0[5], AIO P0[7], AI Vdd P0[6], AI P0[4], AI NC P2[7] P2[5] AI, P2[3] AI, P2[1] Vss SMP I2C SCL, P1[7] I2C SDA, P1[5] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 IO IO IO IO Power Power I I P2[3] P2[1] Vss SMP P1[7] P1[5] NC P1[3] P1[1] Vss P1[0] P1[2] P1[4] NC P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] NC P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL) I2C Serial Data (SDA) No connection. Do not use. Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) No connection. Do not use. Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) External Voltage Reference (VRef) Analog column mux input. Analog column mux input. No connection. Do not use. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. MLF (Top View) LEGEND: A = Analog, I = Input, and O = Output. * The MLF package has a center pad that must be connected to ground (Vss). September 8, 2004 Document No. 38-12028 Rev. *B NC P1[3] I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] NC 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] 11 2. Register Reference This chapter lists the registers of the CY8C24x23A PSoC device. For detailed register information, reference the PSoCTM Mixed Signal Array Technical Reference Manual. 2.1 2.1.1 Register Conventions Abbreviations Used 2.2 Register Mapping Tables The register conventions specific to this section are listed in the following table. Convention R W L C # The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific September 8, 2004 Document No. 38-12028 Rev. *B 12 CY8C24x23A Final Data Sheet 2. Register Reference Register Map Bank 0 Table: User Space Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00DR0 20 # AMX_IN 60 RW DBB00DR1 21 W 61 DBB00DR2 22 RW 62 DBB00CR0 23 # ARF_CR 63 RW DBB01DR0 24 # CMP_CR0 64 # DBB01DR1 25 W ASY_CR 65 # DBB01DR2 26 RW CMP_CR1 66 RW DBB01CR0 27 # 67 DCB02DR0 28 # 68 DCB02DR1 29 W 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # 6C DCB03DR1 2D W 6D DCB03DR2 2E RW 6E DCB03CR0 2F # 6F 30 ACB00CR3 70 RW 31 ACB00CR0 71 RW 32 ACB00CR1 72 RW 33 ACB00CR2 73 RW 34 ACB01CR3 74 RW 35 ACB01CR0 75 RW 36 ACB01CR1 76 RW 37 ACB01CR2 77 RW 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # RW # RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL # # September 8, 2004 Document No. 38-12028 Rev. *B 13 CY8C24x23A Final Data Sheet 2. Register Reference Register Map Bank 1 Table: Configuration Space Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 RW DBB00IN 21 RW CLK_CR1 61 RW DBB00OU 22 RW ABF_CR0 62 RW 23 AMD_CR0 63 RW DBB01FN 24 RW 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 RW 27 ALT_CR0 67 RW DCB02FN 28 RW 68 DCB02IN 29 RW 69 DCB02OU 2A RW 6A 2B 6B DCB03FN 2C RW 6C DCB03IN 2D RW 6D DCB03OU 2E RW 6E 2F 6F 30 ACB00CR3 70 RW 31 ACB00CR0 71 RW 32 ACB00CR1 72 RW 33 ACB00CR2 73 RW 34 ACB01CR3 74 RW 35 ACB01CR0 75 RW 36 ACB01CR1 76 RW 37 ACB01CR2 77 RW 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 E5 E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF RW RW RW RW RW RW RW RW RW RW RW R W W RW W RL # # September 8, 2004 Document No. 38-12028 Rev. *B 14 3. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. Refer to Table 3-20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. SLIMO Mode=1 4.75 Vdd Voltage 3.00 2.40 93 kHz 3 MHz CPU Frequency 12 MHz 24 MHz 4.75 Vdd Voltage SLIMO Mode = 0 5.25 5.25 SLIMO Mode=0 Figure 3-1a. Voltage versus CPU Frequency The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure Symbol oC degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square lid ng Va rati n pe io O Reg Unit of Measure Symbol W 3.60 3.00 SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1 93 kHz 6 MHz IMO Frequency 12 MHz 24 MHz 2.40 Figure 3-1b. IMO Frequency Trim Options Unit of Measure micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts ohm pico ampere pico farad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms mA ms mV nA ns nV pA pF pp ppm ps sps V September 8, 2004 Document No. 38-12028 Rev. *B 15 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.1 Symbol TSTG TA Vdd VIO VIOZ IMIO ESD LU Absolute Maximum Ratings Description Storage Temperature Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current Min -55 -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 - - - - - - - - - Typ Max +100 +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 - 200 Units oC o Table 3-2. Absolute Maximum Ratings Notes Higher storage temperatures will reduce data retention time. C V V V mA V mA Human Body Model ESD 3.2 Symbol TA TJ Operating Temperature Description Ambient Temperature Junction Temperature Min -40 -40 - - Typ Max +85 +100 o Table 3-3. Operating Temperature Units C The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 45. The user must limit the power consumption to comply with this requirement. Notes oC September 8, 2004 Document No. 38-12028 Rev. *B 16 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3 3.3.1 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-4. DC Chip-Level Specifications Symbol Vdd IDD Supply Voltage Supply Current Description Min 2.4 - - 5 Typ Max 5.25 8 V mA Units Notes See DC POR and LVD specifications, Table 318 on page 27. Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 0.75 MHz, 48 MHz = Disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC, analog power = off. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC TA 55 oC, IDD3 Supply Current - 3.3 6.0 mA IDD27 Supply Current when IMO = 6 MHz using SLIMO mode. - 2 4 mA ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.a Reference Voltage (Bandgap) Reference Voltage (Bandgap) - 3 6.5 A ISBH - 4 25 A ISBXTL - 4 7.5 A analog power = off. ISBXTLH - 5 26 A Conditions are with properly loaded, 1W max, 32.768 kHz crystal. Vdd = 3.3 V, 55 oC < TA 85 o C, analog power = off. VREF VREF27 1.28 1.16 1.30 1.30 1.33 1.33 V V Trimmed for appropriate Vdd. Vdd > 3.0V. Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V. a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. September 8, 2004 Document No. 38-12028 Rev. *B 17 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3.2 DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-5. 5V and 3.3V DC GPIO Specifications Symbol RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level Description 4 4 Vdd - 1.0 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. Vdd = 3.0 to 5.25 Vdd = 3.0 to 5.25 Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes VOL Low Output Level - - 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 V V - - 10 10 mV nA pF pF Table 3-6. 2.7V DC GPIO Specifications Symbol RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level Description 4 4 Vdd - 0.4 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 2 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget). IOL = 11.25 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget). Vdd = 2.4 to 3.0 Vdd = 2.4 to 3.0 Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes VOL VIL VIH VH IIL CIN COUT Low Output Level Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - - 2.0 - - - - - - - 90 1 3.5 3.5 0.75 0.8 - - - 10 10 V V V mV nA pF pF September 8, 2004 Document No. 38-12028 Rev. *B 18 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-7. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) - - - - - - 0.0 0.5 1.6 1.3 1.2 7.0 20 4.5 - - 10 8 7.5 35.0 - 9.5 Vdd Vdd - 0.5 mV mV mV V/oC Min Typ Max Units Notes pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. GOLOA Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 - - - - - - - - - 64 - - dB VOHIGHOA High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High - - - - - - 150 300 600 1200 2400 4600 - - - - 0.2 0.2 0.5 200 400 800 1600 3200 6400 - V V V V V V A A A A A A VOLOWOA Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = High Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio dB 0V VIN (Vdd - 2.30) or (Vdd - 1.25V) VIN Vdd. September 8, 2004 Document No. 38-12028 Rev. *B 19 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-8. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range - - - 0.2 7.0 20 4.5 - 35.0 - 9.5 Vdd - 0.2 V/oC Min - - Typ 1.65 1.32 10 8 Max Units mV mV Notes pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. GOLOA Open Loop Gain Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - - - - - 64 - - dB VOHIGHOA High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High is 5V only - - - - - - 150 300 600 1200 2400 4600 - - - - 0.2 0.2 0.2 200 400 800 1600 3200 6400 - V V V V V V A A A A A A VOLOWOA Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio dB 0V VIN (Vdd - 2.30) or (Vdd - 1.25V) VIN Vdd. September 8, 2004 Document No. 38-12028 Rev. *B 20 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-9. 2.7V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range - - - 0.2 7.0 20 4.5 - 35.0 - 9.5 Vdd - 0.2 V/oC Min - - Typ 1.65 1.32 10 8 Max Units mV mV Notes pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. GOLOA Open Loop Gain Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - - - - - 64 - - dB VOHIGHOA High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High is 5V only - - - - - - 150 300 600 1200 2400 4600 - - - - 0.2 0.2 0.2 200 400 800 1600 3200 6400 - V V V V V V A A A A A A VOLOWOA Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio dB 0V VIN (Vdd - 2.30) or (Vdd - 1.25V) VIN Vdd. September 8, 2004 Document No. 38-12028 Rev. *B 21 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3.4 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-10. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - - 52 1.1 2.6 - 5.1 8.8 - mA mA dB VOUT > (Vdd - 1.25) - - - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 V V - - 1 1 - - - - Min - - 0.5 3 +6 - Typ 12 - Max Units mV V/C Notes Vdd - 1.0 V 0.5 x Vdd + 1.1 - 0.5 x Vdd + 1.1 - V V Table 3-11. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - 52 0.8 2.0 - 2.0 4.3 - mA mA dB VOUT > (Vdd - 1.25) - - - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 V V 0.5 x Vdd + 1.0 - 0.5 x Vdd + 1.0 - - - V V - - 1 1 - - Min - - 0.5 3 +6 - Typ 12 - Max Units mV V/C Notes Vdd - 1.0 V September 8, 2004 Document No. 38-12028 Rev. *B 22 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-12. 2.7V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - 52 0.8 2.0 - 2.0 4.3 - mA mA dB VOUT > (Vdd - 1.25) - - - - 0.5 x Vdd - 0.7 0.5 x Vdd - 0.7 V V 0.5 x Vdd + 0.2 - 0.5 x Vdd + 0.2 - - - V V - - 1 1 - - Min - - 0.5 3 +6 - Typ 12 - Max Units mV V/C Notes Vdd - 1.0 V September 8, 2004 Document No. 38-12028 Rev. *B 23 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3.5 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-13. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V VPUMP 3V VPUMP 2V IPUMP Description 5V Output Voltage from Pump 3.3V Output Voltage from Pump 2.6V Output Voltage from Pump Available Output Current VBAT = 1.8V, VPUMP = 5.0V VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.3V, VPUMP = 2.55V VBAT5V VBAT3V VBAT2V VBATSTART VPUMP_Line Min 4.75 3.00 2.45 Typ 5.0 3.25 2.55 Max 5.25 3.60 2.80 V V V Units Notes Configuration of footnote a. Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote a. Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote a. Average, neglecting ripple. SMP trip voltage is set to 2.55V. Configuration of footnote a. 5 8 8 1.8 1.0 1.0 1.2 - - - - - - - - - - 5.0 3.3 3.0 - mA mA mA V V V V SMP trip voltage is set to 5.0V. SMP trip voltage is set to 3.25V. SMP trip voltage is set to 2.55V. Configuration of footnote a. SMP trip voltage is set to 5.0V. Configuration of footnote a. SMP trip voltage is set to 3.25V. Configuration of footnote a. SMP trip voltage is set to 2.55V. Configuration of footnote a. 0oC TA 100. 1.25V at TA = -40oC. Configuration of footnote a. VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-18 on page 27. Configuration of footnote a. VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-18 on page 27. Configuration of footnote a. Load is 5 mA. Configuration of footnote a. Load is 5 mA. SMP trip voltage is set to 3.25V. Input Voltage Range from Battery Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) - 5 - %VO VPUMP_Load Load Regulation - 5 - %VO VPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) Efficiency Efficiency Switching Frequency Switching Duty Cycle - 35 100 50 - - mVpp % E3 E2 FPUMP DCPUMP - - 1.3 50 - - MHz % a. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 3-2. D1 Vdd VPUMP L1 VBAT + SMP Battery PSoCTM Vss C1 Figure 3-2. Basic Switch Mode Pump Circuit September 8, 2004 Document No. 38-12028 Rev. *B 24 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3.6 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 3-14. 5V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Description Bandgap Voltage Reference 1.28 Vdd/2 - 0.04 2 x BG - 0.048 P2[4] - 0.011 BG - 0.009 1.6 x BG - 0.022 -0.034 Min 1.30 Vdd/2 - 0.01 2 x BG - 0.030 P2[4] BG + 0.008 1.6 x BG - 0.010 0.000 Typ 1.33 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.016 1.6 x BG + 0.018 0.034 Max V V V V V V V V V V V V V V V V V V Units Vdd/2 + BG - 0.10 3 x BG - 0.06 2 x BG + P2[6] - 0.113 P2[4] + BG - 0.130 P2[4] + P2[6] - 0.133 3.2 x BG - 0.112 Vdd/2 + BG 3 x BG 2 x BG + P2[6] - 0.018 P2[4] + BG - 0.016 P2[4] + P2[6] - 0.016 3.2 x BG Vdd/2 + BG + 0.10 3 x BG + 0.06 2 x BG + P2[6] + 0.077 P2[4] + BG + 0.098 P2[4] + P2[6]+ 0.100 3.2 x BG + 0.076 Vdd/2 - BG - 0.04 BG - 0.06 2 x BG - P2[6] - 0.084 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.057 Vdd/2 - BG + 0.024 BG 2 x BG - P2[6] + 0.025 P2[4] - BG + 0.026 P2[4] - P2[6] + 0.026 Vdd/2 - BG + 0.04 BG + 0.06 2 x BG - P2[6] + 0.134 P2[4] - BG + 0.107 P2[4] - P2[6] + 0.110 Table 3-15. 3.3V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Column to Column Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Description Bandgap Voltage Reference 1.28 Vdd/2 - 0.03 Not Allowed P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.027 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.075 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092 V P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V P2[4] + 0.001 BG + 0.005 1.6 x BG - 0.010 0.000 P2[4] + 0.009 BG + 0.015 1.6 x BG + 0.018 0.034 V V V mV Min 1.30 Vdd/2 - 0.01 Typ 1.33 Vdd/2 + 0.005 Max V V Units September 8, 2004 Document No. 38-12028 Rev. *B 25 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-16. 2.7V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Column to Column Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Description Bandgap Voltage Reference 1.16 Vdd/2 - 0.03 Not Allowed P2[4] - 0.01 BG - 0.01 Not Allowed -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.08 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.05 P2[4]- P2[6] + 0.01 P2[4] - P2[6] + 0.09 V P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06 V 0.000 0.034 mV P2[4] BG P2[4] + 0.01 BG + 0.015 V V Min 1.30 Vdd/2 - 0.01 Typ 1.33 Vdd/2 + 0.01 Max V V Units 3.3.7 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-17. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) - - Min 80 Typ 12.2 - - Max fF Units k Notes September 8, 2004 Document No. 38-12028 Rev. *B 26 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3.8 DC POR, SMP, and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical Reference Manual for more information on the VLT_CR register. Table 3-18. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.500 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.550 3.02 3.10 3.250 4.64 4.73 4.82 5.00 2.62c 3.09 3.16 3.32d 4.74 4.83 4.92 5.12 V V0 V0 V0 V0 V V V 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.450 2.920 3.02 3.13 4.48 4.64 4.73 4.81 2.51a 2.99b 3.09 3.20 4.55 4.75 4.83 4.95 V0 V0 V0 V0 V0 V V V - Description Vdd Value for PPOR Trip 2.36 2.82 4.55 2.40 2.95 4.70 V V V Min Typ Max Units Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. a. b. c. d. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply. Always greater than 50 mV above VLVD0. Always greater than 50 mV above VLVD3. September 8, 2004 Document No. 38-12028 Rev. *B 27 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.3.9 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-19. DC Programming Specifications Symbol VddIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a - - 2.1 - - - Vdd - 1.0 50,000 1,800,000 10 Min 2.70 - 5 - - - - - - - - - Typ - 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Max V mA V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull-down resistor. Driving internal pull-down resistor. Units Notes Flash Data Retention a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. September 8, 2004 Document No. 38-12028 Rev. *B 28 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.4 3.4.1 AC Electrical Characteristics AC Chip-Level Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-20. 5V and 3.3V AC Chip-Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 24 Typ Max 24.6 a,b,c Units MHz Notes Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 15. SLIMO Mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 15. SLIMO Mode = 1. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b,c MHz FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWSLOW CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm 0.93 0.93 0 0 15 - - - 0.5 0.5 - - 24 12 48 24 32 32.768 23.986 - - - 1700 2800 24.6a,b 12.3b,c 49.2a,b,d 24.6b, d 64 - - 600 10 50 2620 3800 MHz MHz MHz MHz kHz kHz MHz ps ms ms ms ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC. Accuracy is capacitor and crystal dependent. 50% duty cycle. Is a multiple (x732) of crystal frequency. Refer to the AC Digital Block Specifications below. TOS TOSACC Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1P Jitter24M1R FMAX TRAMP 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Peak-to-Peak 24 MHz Period Jitter (IMO) Root Mean Squared Maximum frequency of signal on row input or row output. Supply Ramp Time - 10 40 - 46.8 - - - 0 100 - 50 50 48.0 300 - - - 600 12.3 - - 60 - 49.2a,c ns s % kHz MHz ps ps MHz s Trimmed. Utilizing factory trim values. a. b. c. d. 4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules. September 8, 2004 Document No. 38-12028 Rev. *B 29 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-21. 2.7V AC Chip-Level Specifications Symbol FIMO12 Description Internal Main Oscillator Frequency for 12 MHz Min 11.5 12 Typ Max 12.7a,b,c Units MHz Notes Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 15. SLIMO Mode = 1. Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 15. SLIMO Mode = 1. Refer to the AC Digital Block Specifications below. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b,c MHz FCPU1 FBLK27 F32K1 Jitter32k TXRST DC12M Jitter12M1P Jitter12M1R FMAX TRAMP CPU Frequency (2.7V Nominal)0 Digital PSoC Block Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency 32 kHz Period Jitter External Reset Pulse Width 12 MHz Duty Cycle 12 MHz Period Jitter (IMO) Peak-to-Peak 12 MHz Period Jitter (IMO) Root Mean Squared Maximum frequency of signal on row input or row output. Supply Ramp Time 0.930 0 8 - 10 40 - - - 0 30 12 32 150 - 50 340 - - - 3.15a,b 12.7 96 - 60 600 12.7 - a,b,c MHz0 MHz0 kHz ns s % ps ps MHz s a. 2.4V < Vdd < 3.0V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on maximum frequency for User Modules. PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 3-3. PLL Lock Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram September 8, 2004 Document No. 38-12028 Rev. *B 30 CY8C24x23A Final Data Sheet 3. Electrical Specifications 32K Select TOS 32 kHz F32K2 Figure 3-5. External Crystal Oscillator Startup Timing Diagram Jitter24M1 F24M Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram Jitter32k F32K2 Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram September 8, 2004 Document No. 38-12028 Rev. *B 31 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.4.2 AC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-22. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 10 10 Min - - - 27 22 Typ 12 18 18 - - Max Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Table 3-23. 2.7V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 6 6 18 18 Min - - - 40 40 Typ 3 50 50 120 120 Max Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Figure 3-8. GPIO Timing Diagram September 8, 2004 Document No. 38-12028 Rev. *B 32 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.4.3 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V and 2.7V. Table 3-24. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.75 3.1 5.4 - - - - 100 - - - - MHz MHz MHz nV/rt-Hz 0.01 0.5 4.0 - - - - - - V/s V/s V/s 0.15 1.7 6.5 - - - - - - V/s V/s V/s - - - - - - 5.9 0.92 0.72 s s s Min Typ Max Units Notes - - - - - - 3.9 0.72 0.62 s s s Table 3-25. 3.3V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.67 2.8 - - - 100 - - - MHz MHz nV/rt-Hz 0.24 1.8 - - - - V/s V/s 0.31 2.7 - - - - V/s V/s - - - - 5.41 0.72 s s Min Typ Max Units Notes - - - - 3.92 0.72 s s September 8, 2004 Document No. 38-12028 Rev. *B 33 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-26. 2.7V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High TSOA Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.67 2.8 - - - 100 - - - MHz MHz nV/rt-Hz 0.24 1.8 - - - - V/s V/s 0.31 2.7 - - - - V/s V/s - - - - 5.41 0.72 s s Min Typ Max Units Notes - - - - 3.92 0.72 s s 3.4.4 AC Digital Block Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-27. 5V and 3.3V AC Digital Block Specifications Function Timer Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 20 50a 50a - - - - - 50a - - - - - - - - - - - - - - - - 49.2 49.2 24.6 8.2 4.1 - 24.6 24.6 ns ns ns MHz MHz MHz MHz ns ns MHz MHz Maximum data rate at 3.08 MHz due to 8 x over Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Description Min 50a - - 50a - - - - - - - - Typ - 49.2 24.6 - 49.2 24.6 Max Units ns MHz MHz ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Notes clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). September 8, 2004 Document No. 38-12028 Rev. *B 34 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-28. 2.7V AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency Capture Pulse Width Maximum Frequency, With or Without Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode 0 Min Typ Max 12.7 Units MHz ns MHz ns MHz MHz 2.4V < Vdd < 3.0V. Notes 100a - 100 - - a -0 - - - - 0 -0 12.7 - 0 12.7 12.7 20 100a 100 - - - - - 100a - - a - -0 - - - - - - -0 - - 0 - -0 - 0 ns ns ns MHz MHz MHz MHz ns ns MHz MHz Maximum data rate at 1.59 MHz due to 8 x over Maximum data rate at 3.17 MHz due to 2 x over clocking. Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 12.7 12.7 12.7 6.35 4.23 -0 12.7 12.7 clocking. Maximum data rate at 1.59 MHz due to 8 x over clocking. a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). September 8, 2004 Document No. 38-12028 Rev. *B 35 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.4.5 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-29. 5V AC Analog Output Buffer Specifications Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 300 300 - - - - kHz kHz 0.8 0.8 - - - - MHz MHz 0.65 0.65 - - - - V/s V/s 0.65 0.65 - - - - V/s V/s - - - - 2.2 2.2 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - Min - - Typ Max 2.5 2.5 Units s s Notes Table 3-30. 3.3V AC Analog Output Buffer Specifications Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 200 200 - - - - kHz kHz 0.7 0.7 - - - - MHz MHz 0.5 0.5 - - - - V/s V/s 0.5 0.5 - - - - V/s V/s - - - - 2.6 2.6 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - Min - - Typ Max 3.8 3.8 Units s s Notes September 8, 2004 Document No. 38-12028 Rev. *B 36 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-31. 2.7V AC Analog Output Buffer Specifications Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 180 180 - - - - kHz kHz 0.6 0.6 - - - - MHz MHz 0.4 0.4 - - - - V/s V/s 0.4 0.4 - - - - V/s V/s - - - - 3 3 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - Min - - Typ 4 4 Max Units s s Notes 3.4.6 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-32. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 - - - - Typ Max 24.6 5300 - - Units MHz ns ns s Notes Table 3-33. 3.3V AC External Clock Specifications Symbol FOSCEXT FOSCEXT - - - Description Frequency with CPU Clock divide by 1a Min 0.093 0.186 41.7 41.7 150 - - - - - Typ Max 12.3 24.6 5300 - - Units MHz MHz ns ns s Notes Frequency with CPU Clock divide by 2 or greaterb High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. September 8, 2004 Document No. 38-12028 Rev. *B 37 CY8C24x23A Final Data Sheet 3. Electrical Specifications Table 3-34. 2.7V AC External Clock Specifications Symbol FOSCEXT FOSCEXT - - - Description Frequency with CPU Clock divide by 1a Frequency with CPU Clock divide by 2 or greaterb High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch Min 0.093 0.186 41.7 41.7 150 - - - - - Typ Max 12.3 12.3 5300 - - Units MHz MHz ns ns s Notes a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. 3.4.7 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-35. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - - - Min - - - - - 20 20 - - - Typ 20 20 - - 8 - - 45 50 70 Max Units ns ns ns ns MHz ms ms ns ns ns Vdd > 3.6 3.0 Vdd 3.6 2.4 Vdd 3.0 Notes September 8, 2004 Document No. 38-12028 Rev. *B 38 CY8C24x23A Final Data Sheet 3. Electrical Specifications 3.4.8 AC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-36. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Description 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Min - - - - - - - - - Max 100 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0 a Fast Mode Min - - - - - - - - 50 Max 400 Units kHz s s s s s Notes ns s s ns a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Table 3-37. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported) Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Description 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Min - - - - - - - - - Max 100 - - - - - - - - - - Fast Mode Min - - - - - - - - - - Max Units kHz s s s s s Notes ns s s ns SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus September 8, 2004 Document No. 38-12028 Rev. *B 39 4. Packaging Information This chapter illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. 4.1 Packaging Dimensions 51-85075 - *A Figure 4-1. 8-Lead (300-Mil) PDIP September 8, 2004 Document No. 38-12028 Rev. *B 40 CY8C24x23A Final Data Sheet 4. Packaging Information 51-85066 *B 51-85066 - *C Figure 4-2. 8-Lead (150-Mil) SOIC 20-Lead (300-Mil) Molded DIPP5 51-85011-A 51-85011 - *A Figure 4-3. 20-Lead (300-Mil) Molded DIP September 8, 2004 Document No. 38-12028 Rev. *B 41 CY8C24x23A Final Data Sheet 4. Packaging Information 51-85077 - *C Figure 4-4. 20-Lead (210-Mil) SSOP 51-85024 - *B Figure 4-5. 20-Lead (300-Mil) Molded SOIC September 8, 2004 Document No. 38-12028 Rev. *B 42 CY8C24x23A Final Data Sheet 4. Packaging Information 51-85014 - *D Figure 4-6. 28-Lead (300-Mil) Molded DIP 51-85079 - *C Figure 4-7. 28-Lead (210-Mil) SSOP September 8, 2004 Document No. 38-12028 Rev. *B 43 CY8C24x23A Final Data Sheet 4. Packaging Information 51-85026 - *C Figure 4-8. 28-Lead (300-Mil) Molded SOIC X = 138 MIL Y = 138 MIL 32 51-85188 - ** Figure 4-9. 32-Lead (5x5 mm) MLF September 8, 2004 Document No. 38-12028 Rev. *B 44 CY8C24x23A Final Data Sheet 4. Packaging Information 4.2 Thermal Impedances Typical JA * 123 oC/W 185 oC/W 109 oC/W 117 oC/W 81 oC/W 69 oC/W 101 oC/W 74 oC/W 22 oC/W Table 4-1. Thermal Impedances per Package Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 MLF * TJ = TA + POWER x JA 4.3 Capacitance on Crystal Pins Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 MLF Package Capacitance 2.8 pF 2.0 pF 3.0 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF 2.0 pF Table 4-2: Typical Package Capacitance on Crystal Pins September 8, 2004 Document No. 38-12028 Rev. *B 45 5. Ordering Information The following table lists the CY8C24x23A PSoC device family's key package features and ordering codes. Table 5-1. CY8C24x23A PSoC Device Key Features and Ordering Information Analog Outputs Analog Blocks (Columns of 3) Digital IO Pins Analog Inputs Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range 8 Pin (300 Mil) DIP 8 Pin (150 Mil) SOIC 8 Pin (150 Mil) SOIC (Tape and Reel) 20 Pin (300 Mil) DIP 20 Pin (210 Mil) SSOP 20 Pin (210 Mil) SSOP (Tape and Reel) 20 Pin (300 Mil) SOIC 20 Pin (300 Mil) SOIC (Tape and Reel) 28 Pin (300 Mil) DIP 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 28 Pin (300 Mil) SOIC 28 Pin (300 Mil) SOIC (Tape and Reel) 32 Pin (5x5 mm) MLF CY8C24123A-24PXI CY8C24123A-24SXI CY8C24123A-24SXIT CY8C24223A-24PXI CY8C24223A-24PVXI CY8C24223A-24PVXIT CY8C24223A-24SXI CY8C24223A-24SXIT CY8C24423A-24PXI CY8C24423A-24PVXI CY8C24423A-24PVXIT CY8C24423A-24SXI CY8C24423A-24SXIT CY8C24423A-24LFXI 4 4 4 4 4 4 4 4 4 4 4 4 4 4 256 256 256 256 256 256 256 256 256 256 256 256 256 256 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 16 16 16 16 16 24 24 24 24 24 24 4 4 4 8 8 8 8 8 10 10 10 10 10 10 2 2 2 2 2 2 2 2 2 2 2 2 2 2 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 5.1 Ordering Code Definitions Package Type: PX = PDIP Pb Free SX = SOIC Pb Free PVX = SSOP Pb Free LFX = MLF Pb Free AX = TQFP Pb Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended CY 8 C 24 xxx-SPxx September 8, 2004 Document No. 38-12028 Rev. *B XRES Pin Ordering Code Package Flash (Kbytes) RAM (Bytes) 46 6. Sales and Company Information To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to the section titled "Getting Started" on page 4 in this document. Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: Facsimile: Web Sites: 800.669.0557 425.787.4641 Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm 6.1 Revision History CY8C24123A, CY8C24223A, and CY8C24423A PSoC Mixed Signal Array Final Data Sheet Table 6-1. CY8C24x23A Data Sheet Revision History Document Title: Document Number: 38-12028 Revision ** *A *B ECN # 236409 247589 261711 Issue Date See ECN See ECN See ECN Origin of Change SFV SFV HMT Description of Change New silicon and new document - Preliminary Data Sheet. Changed the title to read "Final" data sheet. Updated Electrical Specifications chapter. Input all SFV memo changes. Updated Electrical Specifications chapter. Posting: None Distribution: External/Public 6.2 Copyrights Copyrights and Code Protection (c) Cypress MicroSystems, Inc. 2004. All rights reserved. PSoCTM, PSoC DesignerTM, and Programmable System-on-ChipTM are trademarks of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress MicroSystems. Flash Code Protection Note the following details of the Flash code protection features on Cypress MicroSystems devices. Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress MicroSystems nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products. September 8, 2004 (c) Cypress MicroSystems, Inc. 2004 -- Document No. 38-12028 Rev. *B 47 WWW..COM Copyright (c) Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www..com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www..com |
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